A Novel Approach to Implement a Vedic Multiplier for High Speed Applications

Dasari Sireesha; N.Suresh Babu

doi:https://doi.org/10.14445/22315381/IJETT-V6N4P137

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Volume 6 | Number 1 | Year 2013 | Article Id. IJETT-V6N4P137 | DOI : https://doi.org/10.14445/22315381/IJETT-V6N4P137

A Novel Approach to Implement a Vedic Multiplier for High Speed Applications

Dasari Sireesha , N.Suresh Babu

Citation :

Dasari Sireesha , N.Suresh Babu, "A Novel Approach to Implement a Vedic Multiplier for High Speed Applications," International Journal of Engineering Trends and Technology (IJETT), vol. 6, no. 1, pp. 212-217, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V6N4P137

Abstract

Now-a-days in VLSI technology speed optimization plays a vital role. So designing of high speed devices became necessary to fulfill the end user requirements. Generally the processor designing is mainly depending upon the MAC units. In that particularly multiplier architecture comes under crucial designing. In this paper the VEDIC multiplier (Nikhilam Sutra) which is very ancient multiplier whose importance is discussed. The design of multiplier consists of Radix Selection Unit, Exponent Determinant (ED), Mean Determinant (MD) and Comparator. In this paper the Xilinx ISE EDA Tool is used for synthesis and simulation. Ultimately the multiplier shows the product of the provided inputs with reduced latency along with optimized power estimation.

Keywords

Vedic Mathematics, partial product, Exponent & Mean determinant, Xilinx.

References

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