An Efficient Carry Select Adder with Less Delay and Reduced Area Application

Pandu Ranga Rao; Priyanka Halle

doi:https://doi.org/10.14445/22315381/IJETT-V4I9P111

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Volume 4 | Issue 9 | Year 2013 | Article Id. IJETT-V4I9P111 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I9P111

An Efficient Carry Select Adder with Less Delay and Reduced Area Application

Pandu Ranga Rao , Priyanka Halle

Citation :

Pandu Ranga Rao , Priyanka Halle, "An Efficient Carry Select Adder with Less Delay and Reduced Area Application," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 9, pp. 3766-3770, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I9P111

Abstract

Design of area, high speed and power - efficient data path logic systems forms the largest areas of research in VLSI system design. The addition speed is limited by the time necessary to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in several data - processing processors to p erform fast arithmetic purpose . From the configuration of the CSLA, it is clear that there is scope for decreasing the area and delay in the CSLA. This work uses a simple and an efficient gate - level modificat ion which drastically reduces the area and delay of the CSLA. Based on this modification 16, 32, 64 and 128 - bit square - root Carry Select Adder (SQRT C SLA) architectures have been improved and compared with the regular SQRT CSLA architecture. The proposed design has compact area and delay to a great extent when compared with the regular SQRT CSLA. This work estimates the performance of the planned designs with the regular designs in terms of delay, area and synthesis are implemented in Xilinx FPGA. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Keywords

(ASIC), area-efficient, CSLA, low delay

References

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