Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques

Pankaj Agarwal; Nikhil Saxena; Nikhita Tripathi

doi:https://doi.org/10.14445/22315381/IJETT-V4I5P74

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Volume 4 | Issue 5 | Year 2013 | Article Id. IJETT-V4I5P74 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I5P74

Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques

Pankaj Agarwal , Nikhil Saxena , Nikhita Tripathi

Citation :

Pankaj Agarwal , Nikhil Saxena , Nikhita Tripathi, "Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 5, pp. 1688-1693, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I5P74

Abstract

Low power memory is required today most priority with also high stability. The power is most important factor for today technology so the power reduction for one cell is vital role in memory design techniques. In this paper we introduced some design circuit techniques for low power design. Leakage current in standby mode is the m ajor part of power loss. We concentrate on the technique that to reduced the leakage current in standby mode. The one CMOS transistor leakage current due to various parameter is the vital role of power consumption. The CMOS leakage current at the process level can be decreased by some implement on deep sub micron method. The circuit level technique is reduced power consumption at very high level. In this paper we simulate the 7T SRAM cell using many techniques both circuit level, process level in one cell a s Hybrid cell.

Keywords

SRAM, Threshold Voltage, Circuit techniques, Process Technique

References

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