High secured and area optimized Online Memory Testing for efficient Fault Diagnostic Systems

Takkellapati Venu Gopi; Nelarapu Yelli Mahesh; Ippala Yasodhara Reddy; Mallireddy Leela Krishna Sankara Renuka Reddy; N.veeraiah

doi:https://doi.org/10.14445/22315381/IJETT-V4I2P209

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Volume 4 | Issue 2 | Year 2013 | Article Id. IJETT-V4I2P209 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I2P209

High secured and area optimized Online Memory Testing for efficient Fault Diagnostic Systems

Takkellapati Venu Gopi , Nelarapu Yelli Mahesh , Ippala Yasodhara Reddy , Mallireddy Leela Krishna Sankara Renuka Reddy , N.veeraiah

Citation :

Takkellapati Venu Gopi , Nelarapu Yelli Mahesh , Ippala Yasodhara Reddy , Mallireddy Leela Krishna Sankara Renuka Reddy , N.veeraiah, "High secured and area optimized Online Memory Testing for efficient Fault Diagnostic Systems," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 2, pp. 125-131, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I2P209

Abstract

The main intention of th is project is to recommend a fault diagnoses structure for revealing of any software or hardware or permanent failures in the embedded read only memories. BIST controller, along with row selector and column selector is designed to meet necessities of at speed test thus enabling detection of timing defects. The projected approach offers a simple test flow and does not requ ire intensive communications between a BIST controller and a tester. The system rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is intended to meet requirements of at - speed test thus enabling detection of timing defects.

Keywords

ASICs, DFT, BIST, ATPG

References

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