Design & Implementation Of 32-Bit Risc (MIPS) Processor

Marri Mounika; Aleti Shankar

doi:https://doi.org/10.14445/22315381/IJETT-V4I10P135

Research Article | Open Access | Download PDF

Volume 4 | Issue 10 | Year 2013 | Article Id. IJETT-V4I10P135 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I10P135

Design & Implementation Of 32-Bit Risc (MIPS) Processor

Marri Mounika , Aleti Shankar

Citation :

Marri Mounika , Aleti Shankar, "Design & Implementation Of 32-Bit Risc (MIPS) Processor," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 10, pp. 4466-4474, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I10P135

Abstract

In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions and addressing modes on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. Our proposed RISC MIPS Processor technique sends the machine code to the instruction memory of the soft-core from the software tool through UART. The user should use that software tool to write MIPS assembly code, debug the code and generate the machine code. Also, the software tool is used for establishing UART connection.

Keywords

MIPS, Data Flow, Data Path, Pipeline, RISC, CISC.

References

[1] Zheng-WeiMin, Tang-ZhiZhong. Computer System Structure (The second edition), Tsinghua University Press, 2006.
[2] Pan-Song, Huang-JiYe, SOPC Technology Utility Tutorial, Tsinghua University Press, 2006.
[3] Ramdas, T. Li-Minn Ang and Egan, G., "FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection," in Proc. of IEEE Region 10 Conference, Vol. 1, pp. 36-39, 2004.
[4] Xizhi Li and Tiecai Li, "ECOMIPS: an economic MIPS CPU design on FPGA," in Proc. of the 4th IEEE International Workshop on System-on- Chip for Real-Time Applications, pp. 291-294, 2004.
[5] D. M. Harris and S. L. Harris, Digital Design and Computer Architecture,1st edition, Morgan Kaufmann, 2007, USA.
[6] Balpande, R.S. and Keote, R.S., "Design of FPGA based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor," in Proc. of International Conference on Communication Systems and Network Technologies, pp. 409-413, 2011.
[7] MIPS Technologies, Inc. MIPS32™ Architecture For Programmers Volume II: The MIPS32™ Instruction Set June 9, 2003.