Novel 5 Level Cascaded H-Bridge Multilevel Inverter Topology

AbhishekThakur; RejoRoy; T.V.Dixit

doi:https://doi.org/10.14445/22315381/IJETT-V24P248

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Volume 24 | Number 1 | Year 2015 | Article Id. IJETT-V24P248 | DOI : https://doi.org/10.14445/22315381/IJETT-V24P248

Novel 5 Level Cascaded H-Bridge Multilevel Inverter Topology

AbhishekThakur, RejoRoy, T.V.Dixit

Citation :

AbhishekThakur, RejoRoy, T.V.Dixit, "Novel 5 Level Cascaded H-Bridge Multilevel Inverter Topology," International Journal of Engineering Trends and Technology (IJETT), vol. 24, no. 1, pp. 272-274, 2015. Crossref, https://doi.org/10.14445/22315381/IJETT-V24P248

Abstract

This paper represents Novel 5 level cascade H-bridge multilevel inverter using only 6 switches and two DC power source. The main aim of this paper is to increase number of levels with Reduced Number of Switches and Sources at the output without adding any complication to the power circuit. The main aim of the novel topology is to decrease the lower whole harmonic distortion and high output voltage. In this paper pulse width modulation technique is used to implement this topology which can minimize the total harmonic distortion and enhances the output voltages. The hardware of multilevel Inverter circuits has been done using Proteus-7.8 software. An AVR (ATmega16) microcontroller is used to generate pulses for controlling the multilevel inverter circuit and result are show in DSO (digital Storage Oscilloscope).

Keywords

Cascaded H- bridge multilevel inverter, phase pulse width modulation, Proteus7.8/Simulink software, reduced switches and sources.

References

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