A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic

Mrs. KIRUTHIKA.S.V; Dr. (Mrs.) R. SUDARMANI

doi:https://doi.org/10.14445/22315381/IJETT-V22P207

Research Article | Open Access | Download PDF

Volume 22 | Number 1 | Year 2015 | Article Id. IJETT-V22P207 | DOI : https://doi.org/10.14445/22315381/IJETT-V22P207

A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic

Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI

Citation :

Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI, "A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic," International Journal of Engineering Trends and Technology (IJETT), vol. 22, no. 1, pp. 27-30, 2015. Crossref, https://doi.org/10.14445/22315381/IJETT-V22P207

Abstract

In low power design and high speed applications, a high resolution all digital duty cycle corrector (HR-ADDCC) is proposed. It is used to correct the duty cycle error and to achieve an exact 50% output duty cycle. A reversible multiplexer logic is used to obtain a glitch free circuit, which is more feasible compared to conventional logic gates. In addition, a reversible multiplexer based DCC (Duty Cycle Corrector) is proposed to achieve an exact 50% output duty cycle with low power area and high resolution duty cycle correction. It is suitable for wide operating frequency range in nanometer CMOS technology process.

Keywords

Duty Cycle Corrector (DCC), Delay Locked Loop (DLL), All-Digital Duty Cycle Corrector (ADDCC),Digitally Controlled Delay Line (DCDL).

References

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