A Low Power VLSI Design of an All Digital Phase Locked Loop

Nakkina Vydehi; A. S. Srinivasa Rao

doi:https://doi.org/10.14445/22315381/IJETT-V16P256

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Volume 16 | Number 2 | Year 2014 | Article Id. IJETT-V16P256 | DOI : https://doi.org/10.14445/22315381/IJETT-V16P256

A Low Power VLSI Design of an All Digital Phase Locked Loop

Nakkina Vydehi , A. S. Srinivasa Rao

Citation :

Nakkina Vydehi , A. S. Srinivasa Rao, "A Low Power VLSI Design of an All Digital Phase Locked Loop," International Journal of Engineering Trends and Technology (IJETT), vol. 16, no. 2, pp. 288-292, 2014. Crossref, https://doi.org/10.14445/22315381/IJETT-V16P256

Abstract

Phase locked loop is a familiar circuit for high frequency application and very short interlocking time. In this paper we have implemented and analysed All Digital Phase locked loop (ADPLL), as the present applications requires a low cost , low power and high speed Phase locked loops. The design is synthesized in Xilinx ISE software. This work Implements an ADPLL with Nyquist rate phase detector which is basically a digital multiplier, simulation results proves a very high speed of operation for low frequency ranges and resource utilization on FPGA proves the structure simpler.

Keywords

ADPLL, DCO, FPGA, Loop Filter, Phase Detector, PLL, wireless communications, Xilinx

References

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