Area Efficient Low Power Vedic Multiplier Design Using GDI Technique

Nidhi Pokhriyal; Neelam Rup Prakash

doi:https://doi.org/10.14445/22315381/IJETT-V15P238

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Volume 15 | Number 1 | Year 2014 | Article Id. IJETT-V15P238 | DOI : https://doi.org/10.14445/22315381/IJETT-V15P238

Area Efficient Low Power Vedic Multiplier Design Using GDI Technique

Nidhi Pokhriyal , Neelam Rup Prakash

Citation :

Nidhi Pokhriyal , Neelam Rup Prakash, "Area Efficient Low Power Vedic Multiplier Design Using GDI Technique," International Journal of Engineering Trends and Technology (IJETT), vol. 15, no. 1, pp. 196-199, 2014. Crossref, https://doi.org/10.14445/22315381/IJETT-V15P238

Abstract

Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor adders are designed by merging binary counter property with compressor property. In this paper, transistor level implementation of a Vedic multiplier based on a Vedic sutra, Urdhva Tiryakbhyam, is proposed. Higher order compressors are used in partial product addition stage to get the final result. A power efficient technique, Gate Diffusion input, has been used to design all the leaf cells of the multiplier. The designs are synthesized and analysed using Cadence Virtuoso tool in 180nm technology. When compared with CMOS based multiplier, the proposed multiplier shows 36.05% reduction in area and 31% reduction in power.

Keywords

Compressor, Gate diffusion input technique, multiplier, binary counter, low-power.

References

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