Multi Operation Floating Point Architecture using DADDA Multiplier

Girija Alukuru; Janardhana Raju M; Anilkumar Somasi

doi:https://doi.org/10.14445/22315381/IJETT-V13P278

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Volume 13 | Number 3 | Year 2014 | Article Id. IJETT-V13P278 | DOI : https://doi.org/10.14445/22315381/IJETT-V13P278

Multi Operation Floating Point Architecture using DADDA Multiplier

Girija Alukuru , Janardhana Raju M , Anilkumar Somasi

Citation :

Girija Alukuru , Janardhana Raju M , Anilkumar Somasi, "Multi Operation Floating Point Architecture using DADDA Multiplier," International Journal of Engineering Trends and Technology (IJETT), vol. 13, no. 3, pp. 391-393, 2014. Crossref, https://doi.org/10.14445/22315381/IJETT-V13P278

Abstract

Floating-point unit (FPU) is one of the most important custom applications needed in most hardware designs as it adds accuracy and ease of use. Its applications range from multimedia and 3D graphics processing to scientific and engineering applications. In this thesis we designed a ASIC implementation of a novel single-precision floating point processing element (FPPE) using a 24-b variant is presented for multi operations based on selection such as addition, subtraction, multiplication and accumulation operations. This FPPE can be designed by using 24X24 Dadda multiplier. We also present a circuit-level implementation of the Dadda multiplier to explore the various Performance-speed tradeoffs involved. The proposed floating point architecture is used in the application development of DSP such as Finite impulse response (FIR) filters, graphics processing, Discrete cosine transforms (DCT), fast Fourier transform (FFTs) division and argument reduction.

Keywords

Design of Dadda multiplier, floating point 32-b design, floating point reconfiguration and its rounding.

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